Design and Simulation of Improved SOI SiGe Hetero-Junction Bipolar Transistor Architecture with Strain Engineering

In order to improve the electrical and frequency characteristics of SiGe heterojunction bipolar transistors (HBTs), a novel structure of SOI SiGe heterojunction bipolar transistor is designed in this work. Compared with traditional SOI SiGe HBT, the proposed device structure has smaller window widths of emitter and collector areas. Under the act of additional uniaxial stress induced by Si _0.85Ge _0.15, all the collector region, base region and emitter region are strained, which is beneficial to improve the performance of SiGe HBTs. Employing the SILVACO ^Ⓡ TCAD tools, the numerical simulation results show that the maximum current gain β _max, the Earley voltage V_A are achieved for 1062 and 186 V, respectively, the product of β and V_A, i.e., β × V_A, is 1.975 × 10 ⁵ V and, the peak cutoff frequency f _T is 419 GHz when the Ge component in the base has configured to be a trapezoidal distribution. The proposed SOI SiGe HBT architecture has a 52.9% improvement in cutoff frequency f _T compared to the conventional SOI SiGe HBTs.

• Uniaxial Strain
• SOI SiGe HBT
• Electrical Performance
• Frequency Performance

1. Introduction

Recently, there has been increased interest in SiGe HBT technology for microwave RF circuits because of its high-frequency and compatibility with silicon technology [1]. Several works have been reported on optimizing the high-frequency of SiGe HBT that can be found from the refs. [2] [3] [4] [5]. Also, the ref. [6] has been proved that reducing the width of the emitter can greatly improve the frequency of SiGe HBT. In addition, the band structure of silicon can be changed by introducing global strain or local strain to improve carrier mobility has been reported [7] [8]. Scholars have improved the performance of SiGe HBT by using stacked metal interconnect structures or introducing mechanical stress [9] [10]. But the reliability is poor, and the process is not easy to control. A SiGe HBT device structure with a virtual substrate was proposed in ref. [11], which effectively improved the current gain. However, the improvement of frequency characteristics is limited, and the self-heating effect of the substrate is significant. Therefore, the introduction of strain engineering can reduce the transit time of carriers in the collector, and effectively improve the frequency characteristics of the device.

In this paper, the proposed device improves the frequency characteristics by introducing stress, and uses SOI substrate structure with buried oxygen layer is used to reduce the self-heating effect brought by virtual substrate. First, the SOI technology and strain silicon technology are combined to introduce uniaxial stress into the SOI collector with N⁺ buried layer to form a new SOI SiGe HBT device structure. Then, the effects of Ge component on the current gain, Early voltage and cut-off frequency are briefly described. Finally, the structure has been proved to be able to achieve breakthroughs in the key frequency characteristics, i.e. f_T > 400 GHz.

2. Device Model and Process Simulation Flow

In this paper, a two-dimensional device model is established by using SILVACO^Ò TCAD tools and the ATHENA module is then employed to simulate the process flow. The proposed device architecture is shown in Figure 1.

The widths of the emitter window and the collector window are 120 nm and 400 nm, respectively, which are following the size-reduction roadmap mentioned in ref. [6]. The characteristics of the device structure are mainly reflected in the stress distribution. Firstly, the strain engineering of “embedded” Si_1−yGe_y source and drain that commonly used in 90 nm, 65 nm and 45 nm CMOS process nodes, is now introduced in the collector region, where uniaxial compressive stress is consequently applied in the horizontal direction. Then, the Si_1−xGe_x base is grown upon the strained collector. Due to the different lattice constants of Si and SiGe, the base region is subject to biaxial compressive stress [12]. According to the principle of elasticity, the collector is uniaxial compressive stressed, and the base is therefore with the act of both the uniaxial and the biaxial stresses. Also, an uniaxial tensile strained cap-layer is sandwiched between poly-silicon and Si_1−xGe_x base to build a double-layer “composite” emitter architecture [13]. The device model parameters are listed in Table 1.

The manufacture process simulation of the proposed SOI SiGe HBT mainly includes the following 6 steps: 1) Initialize (100) p-Si substrate; 2) Buried Oxide layer (BOX) is grown at 850˚C, then n⁺ buried layer and n⁻ collector are sequentially grown upon the BOX layer; 3) Two grooves are etched into the n⁻ collector

Table 1

Structural parameters of SOI SiGe HBT

Region		Parameters
	Material	Thickness (nm)	Doping (cm−3)	Ge component
Strain silicon in Emitter	Si	12	1 × 1018	0
Polysilicon in Emitter	Poly Si	88	1 × 1020	0
Base	Si1−xGex	20	1 × 1019	15 - 30
Collector	Si	60	5 × 1017	0
Collector stress region	Si1−yGey	60	0	15
N+ silicon	Si	20	1 × 1020	0
Buried oxide	Oxide	100	0	0
Silicon substrate	Si	200	1 × 1015	0

layer where uniaxial stress generates or applies, and Si_1−yGe_y is deposited in the etched grooves by selective epitaxy growth (SEG); 4) Electrode area of the collector is etched, and heavily-doped poly-silicon as the reach-through area of the collector is deposited; 5) P-type Si_1−xGe_x base, heavily-doped P-type poly-silicon extrinsic base, and multi-layer emitter are successively deposited, and thin oxide films and poly-silicon are deposited by low-pressure chemical vapor deposition (LPCVD); 6) Aluminum (Al) film is finally produced on the whole surface by vacuum evaporation, any metal regions exterior to the electrodes are then removed by photolithography.

3. The Effect of Germanium (Ge) Profile on Current Gain and Early Voltage

The design of the base region is mainly considered from two aspects, one is the boron doping concentration, the other is the distribution of Ge profile. This paper mainly studies the influence of different Ge profile according to the uniform boron doping concentration in the base region on device performance. The Ge profile in the base region can be classified into three types: box, triangle and trapezoid. Different Ge profile will affect the bandgap of the Si_1−xGe_x base. The bandgap near to the emitter is reasonably configured to be larger than that near to the collector, so the built-in electric field is introduced to accelerate the transport of electrons [14]. The gradient Ge profile generates the acceleration field in the base, and reduces the base transition time, base recombination and increase the current.

Ge profile commonly used in the base of SiGe HBT, X₀ is the boundary of the base near the emitter, X_WB is the boundary of the base near the collector, DE_g (X₀) is the band narrowing caused by Ge mole-fraction at X₀, and DE_g (X_WB) the band narrowing caused by Ge mole-fraction at X_WB. The relationship between the graded Ge fraction in the base and the current gain β is obtained by Equation (1) [15].

β SiGe β Si ∝ [ Δ E g , g r a d e / k T ] exp [ Δ E g ( X 0 ) / k T ] 1 − exp [ − Δ E g , g r a d e / k T ] (1)

Δ E g , g r a d e = Δ E g ( X W B ) − Δ E g ( X 0 ) (2)

The ratio of the current gain of SiGe HBT to that of Si BJT β_max/β_Si has an exponential relationship with DE_g (X₀). As shown as Equation (2), it is linear with the bandgap difference DE_{g, grade} caused by the graded Ge profile in the base. It can be seen that the Ge mole-fraction near the emitter has a significant effect on the current gain. The current gain with trapezoidal Ge distribution is larger than that with triangular Ge distribution when the content of Ge component in the base.

According to Equation (3) [15], the relationship between the Early voltage and the Ge component in the base region is proportional to the bandgap difference DE_{g, grade}.

V A,SiGe V A,Si ∝ exp [ − Δ E g , g r a d e / k T ] − 1 Δ E g , g r a d e (3)

The relationship between the current gain and the optimal value of the Early voltage can be obtained [15].

β SiGe ⋅ V A,SiGe β Si ⋅ V A,Si ∝ exp [ Δ E g ( X 0 ) k T ] ⋅ exp [ Δ E g , g r a d e k T ] (4)

According to the above equations, the product of current gain and Early voltage of box Ge profile is smaller than that of Ge component gradient under the base Ge profile is constant.

In the device simulation, V_CE was 1.2 V and V_BE was varied from 0.1 to 1.2 V. The current gain is obtained and compared as shown in Figure 2. Based on the

above device structural model, the effects of three base Ge component distributions on current gain are obtained. It can be seen from the β-V_BE curve exhibited in Figure 2 that, for the Ge profile in the base, the current gains with box and trapezoid distribution are greater than that with the same distribution of conventional SiGe HBTs. Among them, the maximum gain β_max of the box distribution of Ge component in the base is calculated as high as 2415, that of the trapezoid distribution β_max is 1062, and that of the triangle distribution β_max is 273. Therefore, the current gain of box type is the highest, which is following the above theoretical analysis.

Early voltage is one of the important parameters to characterize the electrical characteristics of devices. When the value of the Early voltage is larger, the width modulation effect in the base is smaller, and the concentration gradient of minority carrier in the base increases, hence the current gain β is naturally increased. The extraction of the value of the Early voltage is through the I_C-V_CE curve when I_B is set to be different constant and V_CE is close to zero, the tangent intersects the abscissa value, which corresponds to V_A. Therefore, the smoother the I_C-V_CE curve, the larger the V_A, and the better output characteristics of the device. When the base Ge component of SOI SiGe HBT is trapezoid-distributed, the output characteristic of the device is shown in Figure 3. The I_C-V_CE curves with I_B = 0.05 μA, 0.5 μA, 1 μA and 1.5 μA are selected. The curve is relatively smooth, and the calculated Early voltage V_A is about 186 V.

Figure 4 shows the output characteristic of three different base Ge component distributions when the base current I_B is a fixed value of 1.5 μA, which the influence of Ge component distribution on the output characteristic curve. It can be

seen from the figure that the curve of triangle distribution and trapezoid distribution is relatively smooth, while the curve of box distribution has the largest gradient and the Early voltage is the smallest. The results show that the Early voltage of trapezoid distribution is about 186 V, that of triangle distribution is about 224 V, and that of box distribution is 43 V.

From the simulation results, the maximum values of β × V_A of three Ge component distributions are summarized in Table 2.

It can be concluded that the optimal values of current gain and Early voltage β × V_A are the highest when the base Ge component is trapezoidal.

Table 2

The maximum values of β × V A of three Ge component distributions

	Ge component distributions
	box	trapezoid	triangle
β × VA	1.038 × 105 V	1.975 × 105 V	6.115 × 104 V

4. The Effect of Base Ge Component Distribution on Cut-Off Frequency f T

One of the key parameters to measure the electrical characteristics of devices is the cut-off frequency f_T, the change of Ge composition in the base mainly affects the transition time τ_B and the transition time τ_E in the emission region. Reducing these two-time constants can effectively improve the frequency characteristics of the device. According to Equation (5), when the base Ge component of SiGe HBT is slowly changing, the relationship between base transition time and emitter transition time and base Ge component respectively.

τ B,SiGe τ B,Si ∝ [ 1 − k T / Δ E g , g r a d e ] exp − Δ E g , g r a d e / k T Δ E g , g r a d e (5)

τ E,SiGe τ E,Si ∝ 1 − exp − Δ E g , g r a d e / k T Δ E g , g r a d e exp Δ E g ( X 0 ) / k T (6)

Among them, the DE_{g, grade} is bandgap differences caused by gradient difference with insignificant Ge component variation. From Equation (5) that τ_{B, SiGe} is smaller than τ_{B, Si} due to the existence of bandgap difference. Therefore, the slow change of Ge component in the base region causes the gradual change of energy band to form a built-in electric field to accelerate the electron drift, which shortens the time of minority carrier crossing the base region. According to the formula, when the gradient of Ge component in the base increases, the cutoff frequency f_T will increase. From Equation (6), it can be obviously seen that the ratio of τ_{E, SiGe}/τ_{E, Si} is inversely proportional to the narrowing of the bandgap DE_g (X₀) caused by the Ge component on the side near the emission, and is linear with DE_{g, grade}. Therefore, the key variable affecting the transit time τ_{e, SiGe} of the emitter is DE_g (X₀). When the base Ge component is trapezoid distributed and the concentration of Ge component close to the emitter is not 0, the DE_g (X₀) and DE_{g, grade} increase at the same time. It can effectively reduce the transit time of the emitter, thus increasing the cut-off frequency f_T.

The frequency characteristics of SOI SiGe HBT with different base Ge component distribution are obtained by the ATLAS simulation module as shown in Figure 5. The transit frequency f_T and the maximum oscillation frequency f_max were extracted from s-parameter measurements extrapolating current gain h21 and unilateral gain U. The cut-off frequency f_T is the largest, up to 419 GHz, when V_CE = 4 V and the Ge component in the base is trapezoidal distribution; the cut-off frequency f_T is simulated as the value of 403 GHz when the Ge component is triangular distribution; the cut-off frequency f_T is 398 GHz when the

Ge component is box distribution. In conclusion, the best choice of Ge components in the base for the improvement of SOI SiGe HBT performance is an exactly trapezoidal distribution.

5. The Effect of Uniaxial Stress on Frequency Characteristics f T

The simulation of the electrical characteristics of the small-size SOI SiGe HBT uses the ATLAS two-dimensional device simulation module. The main physical models used in the numerical simulation are concentration-dependent mobility model, parallel electric field dependence model, auger recombination model, Shockley-Read-Hall (SRH) recombination model, Band narrowing model, Stress model, energy balance transmission model and Fermi-Dirac statistical model. Newton iterative method and the Gummel iterative method are also used for numerical calculation.

The collector of SOI SiGe HBT also affects the frequency characteristics of the device, the smaller the delay time τ_c in the collector, the greater the cut-off frequency. This paper innovatively introduces the embedded Si_1−yGe_y source drain strain technology in the collector (as shown in Figure 6). When a stress is applied to the collector, the electrons velocity vertical passing through the collector region increased due to the existence of compressive stress, so the delay time of the collector region will be further reduced. The f_T curves as a function of the collector for HBT device with stress and without stress are shown in Figure 7. The simulation results show that the cut-off frequency f_T of the traditional SOI SiGe HBT (without stress) is 197 GHz, while the improved SOI SiGe HBT (with

stress) is 419 GHz. The cut-off frequency f_T is increased by 52.9%. The improvement of collector optimization frequency is greater than that of base optimization frequency because the base is very thin and the transition time τ_B of the base is limited.

6. Conclusion

The simulation study of SiGe SOI HBT with strain into the collector. When the base Ge component distribution is a trapezoid, the influence of different base Ge component distribution on the SiGe HBT’s characteristics has been simulation and analysis. The maximum value of the current gain β_max is 1062, the value of the Early voltage V_A is 186 V, the product of the Early voltage and the current gain is 1.975 × 10⁵ V, and the maximum value of the cut-off frequency f_T is 419 GHz. The cut-off frequency is increased by 52.9% compared with the device structure without stress. The proposed novel SOI SiGe HBT device is compatible with the CMOS technology and has certain theoretical significance and reference value for the circuit design and process integration of commercial terahertz Si/SiGe BiCMOS in the future.

Acknowledgements

This work was financially supported by the National Natural Science Foundation of China (61704147, 61404019).

Conflicts of Interest

The authors declare no conflicts of interest regarding the publication of this paper.

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